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1 rev. 4408a?aero?02/05 features operating voltage: 3.3v access time: ? 15 ns for 3.3v biased only (at60142f) ? 17 ns for 5v tolerant (at60142ft) very low power consumption ? active: 650 mw (max) @ 15 ns, 540 mw (max) @ 25 ns ? standby: 3.5 mw (typ) wide temperature range: -55 to +125 c ttl-compatible inputs and outputs asynchronous designed on 0.25 m radiation hardened process no single event latch up below let threshold of 80 mev/mg/cm 2 tested up to a total dose of 300 krads (si) according to mil-std-883 method 1019 500 mils wide fp36 package esd better than 4000v for the at60142f esd better than 2000v for the at60142ft quality grades: escc, qml-q or v with smd 5962-05208 description the at60142f/ft are very low power cmos static ram organized as 524 288 x 8 bits. atmel brings the solution to applications where fast computing is as mandatory as low consumption, such as aerospace electronics, portable instruments, or embarked systems. utilizing an array of six transistors (6t) memory cells, the at60142f/ft combine an extremely low standby supply current (typical value = 1 ma) with a fast access time at 15 ns over the full military temperature range. the high stability of the 6t cell provides excellent protection against soft errors due to noise. the f version is biased at 3.3 v and is not 5v tolerant: it is available to 15 ns specification. the ft version is a variant allowing for 5v tolerance: it is available in 17 ns specification. the at60142f/ft are processed according to the methods of the latest revision of the mil prf 38535 or escc 9000. it is produced on a radiation hardened 0.25 m cmos process. rad hard 512k x 8 very low power cmos sram at60142f at60142ft
2 at60142f/ft 4408a?aero?02/05 block diagram pin configuration a0 a1 a2 a3 a4 cs i/o1 i/o2 vcc gnd i/o3 i/o4 we a5 a6 a7 a8 a9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 nc a18 a17 a16 a15 oe i/o8 i/o7 gnd vcc i/o6 i/o5 a14 a13 a12 a11 a10 n/c 36 - pin -flatpack - 500 mils
3 at60142f/ft 4408a?aero?02/05 pin description table 1. pin names table 2. truth table (1) name description a0 - a18 address inputs i/o1 - i/o8 data input/output cs chip select w e write enable oe output enable vcc power supply gnd ground cs w e oe inputs/outputs mode hxx z deselect/ power-down l h l data out read l l x data in write l h h z output disable note: 1. l=low, h=high, x= h or h, z=high impedance.
4 at60142f/ft 4408a?aero?02/05 electrical characteristics absolute maximum ratings* note: 1. 7v for ft version. 2. for at60142f. it is better than 2000v for at60142ft. military operating range recommended dc operating conditions note: 1. ft version: 5.5v in dc, 5.8v in transient conditions. capacitance note: 1. guaranteed but not tested. supply voltage to gnd potential:.........................-0.5v + 4.6v dc input voltage:.....................................gnd -0.5v to 4.6v (1) dc output voltage high z state: ................gnd -0.5v to 4.6v storage temperature: ................................... -65 c to + 150 c output current into outputs (low): ............................... 20 ma electro statics discharge voltage (2) :.. .........> 4000v (mil std 883d method 3015.3) *note: stresses beyond those listed under "absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating voltage operating temperature military 3.3 + 0.3v -55 c to + 125 c parameter description min typ max unit vcc supply voltage 3 3.3 3.6 v gnd ground 0.0 0.0 0.0 v v il input low voltage gnd - 0.3 0.0 0.8 v v ih input high voltage 2.2 ? v cc + 0.3 (1) v parameter description min typ max unit c in (1) input low voltage ? ? 12 pf c out (1) output high voltage ? ? 12 pf
5 at60142f/ft 4408a?aero?02/05 dc parameters consumption parameter description minimum typical maximum unit iix (1) 1. gnd < v in < v cc , gnd < v out < v cc output disabled. 2. ft version only: v in = 5.5v, v out = 5.5v, output disabled. 3. v cc min. i ol = 8 ma. 4. v cc min. i oh = -4 ma. input leakage current -1 ? 1 a ioz (1) output leakage current -1 ? 1 a iih (2) at 5.5v input leakage current -1 ? 10 a iozh (2) at 5.5v output leakage current -1 ? 10 a vol (3) output low voltage ? ? 0.4 v voh (4) output high voltage 2.4 ? ? v symbol description tavav/tavaw test condition at60142f-15 at60142ft-17 unit value i ccsb (1) 1. cs > v ih standby supply current ?2.52.5mamax i ccsb1 (2) 2. cs > v cc - 0.3v 3. f = 1/ tavav , i out = 0 ma, we = oe = v ih , v in = gnd/v cc , v cc max. 4. f = 1/ tavaw , i out = 0 ma, w = v il , oe = v ih , v in = gnd/v cc , v cc max. standby supply current ? 2 2 ma max i ccop (3) read dynamic operating current 15 ns 17 ns 25 ns 50 ns 1 s 180 - 150 75 10 - 170 150 75 10 ma max i ccop (4) write dynamic operating current 15 ns 17 ns 25 ns 50 ns 1 s 150 - 130 120 100 - 145 130 120 100 ma max
6 at60142f/ft 4408a?aero?02/05 ac characteristics temperature range:................................................ -55 +125 c supply voltage:........................................................ 3.3 + 0.3v input pulse levels: .................................................. gnd to 3.0v input rise and fall times:....................................... 3ns (10 - 90%) input and output timing reference levels: ............ 1.5v output loading i ol /i oh :............................................ see figure 1 figure 1. ac test loads waveforms data retention mode atmel cmos ram's are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules insure data retention: 1. during data retention chip select cs must be held high within v cc to v cc -0.2v. 2. output enable (oe ) should be held high to keep the ram outputs high imped- ance, minimizing power dissipation. 3. during power-up and power-down transitions cs and oe must be kept between v cc + 0.3v and 70% of v cc . 4. the ram can begin operation > t r ns after v cc reaches the minimum operation voltages (3v). figure 2. data retention timing
7 at60142f/ft 4408a?aero?02/05 data retention characteristics parameter description min typ t a = 25 cmax unit v ccdr v cc for data retention 2.0 ? ? v t cdr chip deselect to data retention time 0.0 ? ? ns t r operation recovery time t avav (1) 1. t avav = read cycle time. ??ns i ccdr (2) 2. cs = v cc , v in = gnd/v cc . data retention current ? 0.700 1.5 ma
8 at60142f/ft 4408a?aero?02/05 write cycle notes: 1. parameters guaranteed, not tested, with output loading 5 pf. (see ?ac test loads waveforms? on page 6.) read cycle notes: 1. parameters guaranteed, not tested, with output loading 5 pf. (see ?ac test loads waveforms? on page 6.) symbol parameter at60142f-15 at60142ft-17 unit value tavaw write cycle time 15 17 ns min tavwl address set-up time 0 0 ns min tavwh address valid to end of write 8 8 ns min tdvwh data set-up time 7 7 ns min telwh cs low to write end 12 12 ns min twlqz write low to high z (1) 67nsmax twlwh write pulse width 8 8 ns min twhax address hold from end of write 0 0 ns min twhdx data hold time 0 0 ns min twhqx write high to low z (1) 33nsmin symbol parameter at60142f-15 at60142ft-17 unit value tavav read cycle time 15 17 ns min tavqv address access time 15 17 ns max tavqx address valid to low z 5 5 ns min telqv chip-select access time 15 17 ns max telqx cs low to low z (1) 55nsmin tehqz cs high to high z (1) 67nsmax tglqv output enable access time 6 8 ns max tglqx oe low to low z (1) 22nsmin tghqz oe high to high z (1) 56nsmax
9 at60142f/ft 4408a?aero?02/05 figure 3. write cycle 1. w e controlled, oe high during write figure 4. write cycle 2. w e controlled, oe low figure 5. write cycle 3. cs controlled (1) note: the internal write time of the memory is defined by the overlap of cs low and w low. both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. the data input setup and hold timing should be refer- enced to the active edge of the signal that terminates the write. data out is high impedance if oe = v ih . e e e
10 at60142f/ft 4408a?aero?02/05 figure 6. read cycle nb 1: address controlled (cs = oe = v il , we = v ih ) figure 7. read cycle nb 2: chip select controlled (we = v ih )
11 at60142f/ft 4408a?aero?02/05 ordering information note: 1. contact atmel for availability. 2. will be replaced by smd part number when available. part number temperature range speed package flow at60142f-dc15m-e 25 c 15 ns/3.3v fp36.5 engineering samples 5962-0520802qxc -55 to +125c 15 ns/3.3v fp36.5 qml q 5962-0520802vxc -55 to +125c 15 ns/3.3v fp36.5 qml v 5962r0520802vxc -55 to +125c 15 ns/3.3v fp36.5 qml v rha at60142f-dc15ssb -55 to +125 c 15 ns/3.3v fp36.5 escc at60142f-dd15m-e (1) 25 c 15 ns/3.3v die engineering samples at60142f-dd15mmq (1) (2) -55 to +125 c 15 ns/3.3v die qml q at60142f-dd15smv (1) (2) -55 to +125 c 15 ns/3.3v die qml v AT60142FT-DC17M-E 25 c 17 ns/5v tol. fp36.5 engineering samples 5962-0520801qxc -55 to +125 c 17 ns/5v tol. fp36.5 qml q 5962-0520801vxc -55 to +125 c 17 ns/5v tol. fp36.5 qml v 5962r0520801vxc -55 to +125 c 17 ns/5v tol. fp36.5 qml v rha at60142ft-dc17ssb -55 to +125 c 17 ns/5v tol. fp36.5 escc at60142ft-dd17m-e (1) 25 c 17 ns/5v tol. die engineering samples at60142ft-dd17mmq (1) (2) -55 to +125 c 17 ns/5v tol. die qml q at60142ft-dd17smv (1) (2) -55 to +125 c 17 ns/5v tol. die qml v
12 at60142f/ft 4408a?aero?02/05 package drawings 36-lead flat pack (500 mils)
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions locate d on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implicati on. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature 4408a?aero?02/05 /xm ? atmel corporation 2005 . all rights reserved. atmel ? and combinations thereof are the register ed trademarks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of others.

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